Cornell University, College of Engineering
B.S. Electrical and Computer Engineering
Ithaca, New York
23.8 27.5
GlobalFoundries
Software Engineering Intern, EDA Design
26.6 8 Austin, TX
● Collaborated on four person team to build Python based open-source, CMA-ES based compact model flow as alternative to existing licensed modeling tools, giving modelers an additional automated fitting option
● Adapted extraction flow to 12LPPLUS FinFET silicon data, achieving less than 5mV Vt error and less than 5% Id error
● Completed weekly hands on training with digital design team covering synthesis, place-and-route, and timing analysis
● Executed digital implementation flow using Synopsys Design Compiler for synthesis, ICC2 for place and route, StarRC for parasitic extraction, and PrimeTime for static timing analysis of critical timing paths and performance
Software Engineering Intern
25.6 8 Malta, NY
● Automated PDK layout-parameter extraction and preprocessing for Cadence Virtuoso and KLayout, enabling neural-network modeling of parasitic R/C and reducing model delivery TAT by 70%+ across technologies
● Standardized PDK workflows across design teams, improving parameter consistency across legacy and newer PDKs
● Curated training datasets of 1.2M+ circuit layouts for existing ANN model predicting parasitic behavior
● Resolved complex-node extraction failures using pattern-recognition techniques, achieving 100% parameter accuracy
● Device Modeling: HSPICE, SPICE Compact Modeling, CMA-ES Optimization, Parameter Extraction, FinFET Device Characterization
● Programming: Python, C/C++, Java
● ML/Data: Pytorch, ANN Model Training
● Coursework: Computer Architecture, Embedded Operating Systems, Complex Digital ASIC Design
● Campus Involvement: ENGRG 1050 Peer Advisor; Society of Women Engineers Corporate Liaison
I’m in the process of completing my Bachelors in Electrical and Computer Engineering from Cornell University where I have developed a strong foundation in computer architecture, digital hardware design, embedded systems, and ASIC design. My academic and professional experiences have given me hands-on exposure to Verilog, Python, C/C++, FPGA development, semiconductor modeling, and industry-standard EDA tools including Cadence Virtuoso, Quartus, Synopsys Design Compiler, ICC2, StarRC, and PrimeTime. What sets me apart from my peers is my technical experience across both academic and industry projects. My project experience demonstrates passion in hardware engineering including work with RISC-V processors, memory optimization, and embedded systems. During my internships at GlobalFoundries, I contributed to semiconductor modeling and design-automation workflows, working on developing an alternative modeling tool. These experiences illustrate my ability to work across hardware and software and analyze complex te
